The need for voltage multipliers is well recognized in various fields of electronics. In digital watch technology, for example, economic and physical constraints associated with watch design limit the size of the battery which can be retained within the watch. The battery is used to power the watch circuitry as well as the display devices. Generally, a 1.5 volt battery is used. However, higher voltages are required to drive the display devices. For example, potentials of 4 volts and up are needed to drive display devices such as liquid crystal displays. Various circuits have been designed for digital watch use to provide this required higher voltage. Prior art voltage multiplying circuits employ resistors, diodes, inductors and bipolar transistors in resonant transfer circuits. A difficulty with the use of such elements in digital watches is that these elements cannot be intergrated into CMOS circuitry which is generally used in the remainder of the watch circuitry. In addition, these components are relatively expensive when compared with the remainder of the watch electronics.
An improved type of voltage multiplier makes use of a circuit which functions to charge a capacitor and then to connect the capacitor in series with a potential source such as the watch battery to effect voltage multiplication. In such a circuit, voltage multiplication occurs because the potential across a capacitor connected in series with another potential source adds to the potential of the other potential source to thereby increase the output potential of the circuit beyond the potential of the source. It is also known to use several capacitors and transistor switching devices which operate to initially connect the capacitors in parallel to charge them to some value and thereafter change the circuit connection such that the capacitors are connected in series with a potential source to cause the potential stored on the several capacitors to add with the potential produced by the source to develop a higher output potential than that developed by the source itself. When the capacitors are connected in parallel they can charge to essentially the source potential. Thus, the series connected circuit comprised of the source itself and the capacitors will produce an output voltage which is a multiple of the source potential. If two capacitors are used, then a voltage tripler will be developed.
Voltage multipliers of the capacitance type just described are disclosed in U.S. Pat. No. 3,824,447 issued July 16, 1974 to Kuwabara and U.S. Pat. No. 3,975,671 issued Aug. 17, 1976 to Stoll. While these devices present a significant improvement in voltage multiplier circuits for use with digital watches, they suffer certain significant disadvantages. Kuwabara teaches two multiplier designs. In a first design, he makes use of MOS FETs of the same conductivity type. Such a design is not compatible with CMOS devices which are generally used in the remainder of the watch electronics. A further disadvantage of the single conductivity type FET multiplier circuit of Kuwabara involves the fact that it requires gate drive voltages outside the range of the multiplied output voltage if enhancement mode devices are used, or a different set of logic level voltages if depletion mode devices are used. In a second embodiment of the Kuwabara patent, a voltage multiplier using CMOS devices is described. Such a circuit would be compatible with the remainder of the watch electronics; however, the multiplier design requires the use of diodes. A difficulty with this circuit arises because of its use of diodes in the parallel charging path. These will exhibit a forward biased voltage drop on the order of one-half volt. Assuming a 1.5 volt battery, the forward biased voltage drop would amount to one-third of the supply voltage. A still further difficulty with this circuit design involves the fact that no diode with both anode and cathode free of the substrate or not part of a parasitic bipolar transistor is available in ordinary junction isolated CMOS process technology.
The Stoll patent describes a voltage multiplier using CMOS technology. The Stoll design requires that N-channel devices be used to connect the voltage storage capacitors to the negative side of the power supply during the parallel charging part of a cycle of operation. As a result, in order to insure that the body-drain junction does not become forward biased during a negative excursion of the side of the capacitor to which it is connected, the body must be tied to drain. This raises the possibility that, during parallel charging, the body-source junction could become forward biased. If this should happen, a parasitic transistor (consisting of the N substrate which is tied to the positive side of the power supply for a collector, the P well for a base and the N+ source, which is tied to the negative side of the power supply for an emitter) will be turned on and a large spike of current will be drawn from the power supply. If the instantaneous value of this spike is high enough to produce a local voltage drop in the N substrate that is sufficient to forward bias a P-channel source substrate junction, a thyristor section can result. This is a self-sustaining phenomenon and will continue until the power supply voltage drops below the level required to sustain it. A still further disadvantage with the Stoll design involves the use of a clamp circuit to connect the disclosed level shifer to the negative side of the power supply during start up.
Thus there exists a need for a CMOS, capacitance type voltage multiplier which overcomes the disadvantages of the prior art.